Encoding:

Format:

SHRAV[_R].QB 

SHRAV.QB     rd, rt, rs

SHRAV_R.QB   rd, rt, rs

Purpose:

Shift Right Arithmetic Variable Vector of Four Bytes

To execute an arithmetic right shift on four independent bytes by a variable number of bits.

Description:

rd = sign_extend(round(rt31..24 >> rs2..0)) || round(rt23..16 >> rs2..0) || round(rt15..8 >> rs2..0) || round(rt7..0 >> rs2..0)

The four right-most byte elements in register rt are each shifted right arithmetically by sa bits, then written to the corresponding byte elements in destination register rd. The sa argument is provided by the three least-significant bits of register rs, interpreted as an unsigned three-bit integer taking values from zero to seven. The remaining bits of rs are ignored.

In the rounding variant of the instruction, a value of 1 is added at th e most significant discarded bit position of each result prior to writing the rounded result to the destination register.

The sign of the left-most byte result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SHRAV.QB:
   sa2..0 = GPR[rs]2..0
   if ( sa2..0 = 0 ) then
      tempD7..0 = GPR[rt]31..24
      tempC7..0 = GPR[rt]23..16
      tempB7..0 = GPR[rt]15..8
      tempA7..0 = GPR[rt]7..0
   else
      tempD7..0 = ( GPR[rt]31)sa || GPR[rt]31..24+sa )
      tempC7..0 = ( GPR[rt]23)sa || GPR[rt]23..16+sa )
      tempB7..0 = ( GPR[rt]15)sa || GPR[rt]15..8+sa )
      tempA7..0 = ( GPR[rt]7)sa || GPR[rt]7..sa )
   endif
   GPR[rd]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
SHRAV_R.QB:
   sa2..0 = GPR[rs]2..0
   if ( sa2..0 = 0 ) then
      tempD8..0 = ( GPR[rt]31..24 || 0)
      tempC8..0 = ( GPR[rt]23..16 || 0)
      tempB8..0 = ( GPR[rt]15..8 || 0)
      tempA8..0 = ( GPR[rt]7..0 || 0)
   else
      tempD8..0 = ( GPR[rt]31)sa || GPR[rt]31..24+sa-1 ) + 1
      tempC8..0 = ( GPR[rt]23)sa || GPR[rt]23..16+sa-1 ) + 1
      tempB8..0 = ( GPR[rt]15)sa || GPR[rt]15..8+sa-1 ) + 1
      tempA8..0 = ( GPR[rt]7)sa || GPR[rt]7..sa-1 ) + 1
   endif
   GPR[rd]63..0 = (tempD8)32 || tempD8..1 || tempC8..1 || tempB8..1 || tempA8..1

Exceptions:

Reserved Instruction, DSP Disabled